IBM developed the Telum II processor and the Spyre accelerator for the AI ​​operation

IBM has officially introduced its new artificial intelligence chips, including the Telum II processor and Spyre AI accelerators, designed for the IBM Z-series mainframes. These chips significantly accelerate traditional AI tasks and work with large language models on IBM server systems.

The Telum II processor is equipped with eight high-performance cores with a clock frequency of 5.5 GHz. Each core has 36 MB of second-level cache memory, and the total amount of built-in cache memory reaches 360 MB. The virtual cache memory of the fourth level supports the amount of up to 2.88 GB per processor unit, which is 40% more compared to the previous generation. Cores received improved branch prediction, 160 registers and reduced power consumption by 15%.

Telum II is equipped with a built-in AI accelerator that provides high performance output operations with low latency and high throughput. The performance of the accelerator is 24 TOPS per processor, 192 TOPS per block and 768 TOPS per system. In addition to this, the processor includes a new DPU I/O acceleration unit that increases data transfer density by 50%. The chip is manufactured using Samsung’s 5HPP technology and contains 43 billion transistors on a 600mm die.

Spyre accelerators are designed for the enterprise level and provide performance of more than 300 TOPS in AI tasks with 128 GB of LPDDR5 memory. In a system with eight such accelerators, the total memory reaches 1 TB. Each accelerator is equipped with 32 computing cores supporting INT4, INT8, FP8 and FP16 data types, with a power consumption level (TDP) of only 75 W.

IBM plans to begin shipping solutions with Telum II processors to enterprise customers in 2025. Spyre’s accelerators, which are in the early technical version stage, should also go on sale next year.